This disclosure relates to logic analysis.
There are a number of occasions where it is desirable to keep track of the processing activities being performed by data processing apparatus.
It is known to provide logic analysers which switch between a plurality of trigger states, each trigger state corresponding to a state in which one or more hardware signals of the hardware circuitry under test are matched against predetermined values to identify predetermined conditions/states of the hardware circuitry. Such logic analysers can be useful in the context of debugging hardware functionality.
Logic analysers may be applicable to, for example, analysing data handling activity relating to transactions between data handling nodes connected to interconnect circuitry. In this type of environment, individual transactions such as memory accesses may take a period of time between initiation and completion. The transactions may be identified by transaction identifiers while they are in progress.